1. Field of the Invention
The present invention relates to a structure of a voltage downconverter circuit provided in a semiconductor integrated circuit device. In particular, the invention relates to a structure of a voltage downconverter circuit provided in a semiconductor memory device.
2. Description of the Background Art
Semiconductor integrated circuits generally include therein a voltage downconverter circuit (hereinafter referred to as VDC circuit) receiving an external supply voltage ext.Vcc and lowering the voltage to generate an internal supply voltage Int.Vcc for the purpose of reducing power consumption of the circuits.
FIG. 12 is a circuit diagram showing a structure of such a conventional VDC circuit 2000.
Referring to FIG. 12, the conventional VDC circuit 2000 includes a differential amplifier 2100 receiving a reference potential Vref supplied from a reference potential generating circuit (not shown) and a potential on a node nv from which an internal supply potential Int.Vcc is output to provide from a node COMP a result of comparison therebetween, and a P channel driver transistor P1 provided between an external supply potential ext.Vcc and node nv and controlled by the output signal from output node COMP of differential amplifier 2100 to maintain the potential level on node nv equal to reference potential Vref.
Differential amplifier 2100 includes a P channel MOS transistor P11 and an N channel MOS transistor N11 provided in series between external supply potential ext.Vcc and a common node nc, and a P channel MOS transistor P12 and an N channel MOS transistor N12 provided between external supply potential ext.Vcc and common node nc. Between common node nc and a ground potential GND, an N channel MOS transistor N1 is provided having its gate receiving a control signal ACT.
Respective gates of transistors P11 and P12 are connected to each other and the gate and drain of transistor P12 are connected. The gate of transistor N11 receives reference potential Vref and the gate of transistor N12 is connected to node nv.
The connection node between transistors P11 and N11 corresponds to output node COMP of differential amplifier 2100.
Specifically, in this structure, differential amplifier 2100 receives, when signal ACT is in the active state (xe2x80x9cHxe2x80x9d level: the level of external supply potential ext.Vcc) and differential amplifier 2100 is in the active state, reference potential Vref and internal supply potential Int.Vcc as inputs and compares these potentials to accordingly lower a voltage on node COMP if internal supply potential Int.Vcc is lower than reference potential Vref Consequently, driver transistor P1 is activated and control is made to set the potential level on node nv equal to reference potential Vref.
VDC circuit 2000 further includes a P channel MOS transistor P2 provided between external supply potential ext.Vcc and the gate of transistor P1 and receiving signal ACT at its gate.
Transistor P2 prevents internal supply potential Int.Vcc from rising when differential amplifier 2100 is inactive (when signal ACT is at xe2x80x9cLxe2x80x9d level). In other words, if transistor P2 is not provided and differential amplifier 2100 is inactive, a slight amount of current continues flowing to node nv via transistor P1 because the potential on node COMP does not rise to the level of external supply potential ext.Vcc. Consequently, increase of internal supply potential Int.Vcc occurs.
In order to accomplish a stable operation of differential amplifier 2100, a constant current source is required. In the conventional VDC circuit 2000, transistor N1 (hereinafter referred to as constant current source transistor N1) operates as the constant current source. Specifically, transistor N1 is structured to operate as the constant current source for differential amplifier 2100 when it receives signal ACT of the activation level (H level). The activation level of ACT signal for activating the VDC circuit is the level of external supply potential ext.Vcc.
From the opposite point of view, in the active period of a semiconductor integrated circuit device, for example, a semiconductor memory device provided with such a VDC circuit 2000, there is a problem of increase of power consumption since a through current constantly flows through VDC circuit 2000 even if any internal circuit consumes no current (this state is referred to as active standby state).
Further, when the external supply voltage varies (generally a variation of xc2x110% is compensated according to an operational specification), the amount of current flowing through constant current source transistor N1 in differential amplifier 2100 shown in FIG. 12 changes depending greatly on the external supply voltage. If the external supply voltage becomes lower, the amount of current flowing through transistor N1 decreases. This decrease lowers the speed of reducing the voltage on node COMP of differential amplifier 2100, resulting in a problem of deterioration in responsiveness of VDC circuit 2000.
It could be possible to define the drive current of transistor N1 in order to secure a sufficient amount of current even when the external supply voltage is low and thus prevent the responsiveness of the circuit from deteriorating in the event of such a variation in the external supply voltage. However, in this case, if the external supply voltage is high, the amount of current flowing through transistor N1 accordingly increases, resulting in a problem of an excessive through current.
In order to address this problem, Japanese Patent Laying-Open No. 11-3586 discloses a structure of a VDC circuit capable of reducing such a through current as discussed above.
FIG. 13 is a circuit diagram showing the structure of the conventional VDC circuit 3000 disclosed in Japanese Patent Laying-Open No. 11-3586.
VDC circuit 3000 and VDC circuit 2000 shown in FIG. 12 are different in structure as described below.
VDC circuit 3000 includes a differential amplifier 2200 instead of differential amplifier 2100. In differential amplifier 2200, the gate potential of a constant current source transistor N1 is controlled by a reference potential Vref instead of signal ACT controlling the gate potential of constant current source transistor N1 of differential amplifier 2100. In addition, differential amplifier 2200 includes an N channel MOS transistor N2 provided between a common node nc and constant current source transistor N1 to receive a signal ACT at its gate.
The structure as shown in FIG. 13 of VDC circuit 3000 allows the gate potential of constant current source transistor N1 to be controlled by reference potential Vref. Therefore, variation of a through current can be prevented even when the external supply voltage varies.
It should be noted here that a reference potential generating circuit (not shown) for generating reference potential Vref may be defined to operate with a limited low amount of current for the purpose of preventing increase in power consumption since the reference potential generating circuit operates all the time. In this case, if the gate of transistor N1 is connected to the output of reference potential generating circuit as shown in FIG. 13, the reference potential generating circuit has its output connected to an increased load capacitance. As a result, rise of the reference potential after power is applied could be delayed.
In general, a node from which the reference potential is applied is of high impedance. If such a node is frequently used, noise could appear on a line for supplying the reference potential.
Further, when an increased amount of current is consumed that is supplied by internal supply potential Int.Vcc, voltage drop occurs on internal supply potential Int.Vcc. This results in reduction of a potential on an output node COMP of differential amplifier 2200 shown in FIG. 13. At this time, due to a coupling effect by a transistor N11, reduction of reference potential Vref occurs. Therefore, when voltage drop occurs on internal supply potential Int.Vcc, in other words, when differential amplifier 2200 needs a through current most, that through current decreases. A problem thus arises that the performance of VDC circuit 3000 is deteriorated.
On the contrary, when the voltage on internal supply potential Int.Vcc is higher, the amount of through current increases, resulting in an excessive amount of current consumed.
One object of the present invention is to provide a voltage downconverter circuit provided in a semiconductor integrated circuit device, for example, a semiconductor memory device, that is capable of reducing current consumption without deterioration in response rate.
Another object of the invention is to provide a semiconductor memory device including a voltage downconverter circuit capable of reducing current consumption without deterioration in responsiveness.
Briefly, according to one aspect of the invention, the present invention is a voltage downconverter circuit receiving a supply potential and lowering the potential to generate a downconverted potential. The voltage downconverter circuit includes a differential amplifier circuit, a downconverted potential output node, and a drive transistor.
The differential amplifier circuit compares a potential corresponding to a first reference potential with a potential corresponding to the downconverted potential to generate a control signal according to a result of the comparison. The differential amplifier circuit includes a constant current source transistor that receives at its gate a second reference potential supplied through a path different from that of the first reference potential to operate for controlling an operation current value of the differential amplifier circuit.
From the downconverted potential output node, the downconverted potential is supplied.
The drive transistor is provided between the downconverted potential output node and the supply potential to change conductance between the downconverted potential output node and the supply potential in response to the control signal.
According to another aspect of the invention, a semiconductor integrated circuit device includes a memory cell array, a plurality of bit lines and a voltage downconverter circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns for storing data.
The bit lines are provided correspondingly to the columns of the memory cell array.
Each memory cell includes a memory cell capacitor having an insulating layer and a storage node and a cell plate with the insulating layer therebetween, and an access transistor provided between the storage node and a corresponding one of the bit lines for making access to the memory cell.
The voltage downconverter circuit receives a supply potential and lowers the potential to generate a downconverted potential and supplies the downconverted potential to the memory cell.
The voltage downconverter circuit includes a differential amplifier circuit, a downconverted potential output node, and a drive transistor.
The differential amplifier circuit compares a potential corresponding to a first reference potential with a potential corresponding to the downconverted potential to generate a control signal according to a result of the comparison. The differential amplifier circuit includes a constant current source transistor that receives at its gate a second reference potential supplied through a path different from that of the first reference potential to operate for controlling an operation current value of the differential amplifier circuit.
From the downconverted potential output node, the downconverted potential is supplied.
The drive transistor is provided between the downconverted potential output node and the supply potential to change conductance between the downconverted potential output node and the supply potential according to the control signal.
An advantage of the present invention is accordingly that owing to the different paths respectively for transmitting the second reference potential supplied to the constant current source transistor and for transmitting the first reference potential supplied as one input to the differential amplifier circuit, a load capacitance is reduced that should be driven, when power is applied or at like event, by a circuit generating the first and second reference potentials, and thus this reduced load capacitance enables prevention of deterioration in rising characteristics.
Another advantage of the invention is that, owing to a small variation of the operation current of the differential amplifier circuit relative to change in the downconverted voltage and thus stability of the operation current of the differential amplifier circuit, the constant current source transistor can have an optimum size for a circuit operation and thus consumption current can be reduced.
A further advantage of the invention is that, owing to the different paths respectively for transmitting the second reference potential supplied to the constant current source transistor and for transmitting the first reference potential supplied as one input to the differential amplifier circuit, in the voltage downconverter circuit provided in the semiconductor integrated circuit device, a load capacitance is reduced that should be driven, when power is applied, by a circuit generating the first and second reference potentials and thus this reduction enables prevention of deterioration in rising characteristics of the voltage downconverter circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.